Description: Title: Sr. Design Verification Engineer Location: Onsite - Sunnyvale, CA (or) ... and implement IP/SoC verification plans, build verification test benches to enable ... tests based on verification test plan Drive Design Verification to closure based ...
14 days ago
Description: Title: Verification Engineer Location: Sunnyvale, CA Type: Contract ... : The main function of the Verification Engineer is to work with a group ... researchers and engineers to own the electrical system level verification of client ...
7 days ago
... : The main function of the Verification Engineer is to work with a group ... researchers and engineers to own the electrical system level verification of client ... -the-art systems. Using verification skills to define verification requirements, create test ...
6 days ago
Description: Verification Engineer IV Sunnyvale CA (Onsite) 6 months ( ... : The main function of the Verification Engineer is to work with a group ... -the-art systems.The engineer will define verification requirements, create test ca
7 days ago
... Description: Job Title: Senior Design Verification Engineer - Ethernet PHY/PCS Location: ... an experienced Senior Design Verification Engineer with expertise in Ethernet ... - Collaborate with design engineers to resolve verification issues - Strong understa
6 days ago
... years of senior Pre-silicon verification engineer with PCIE physical, link layer ... state of the art of verification techniques, including assertion and ... metric-driven verification. Require familiarity with verification management tools. Prior ...
13 days ago
... are looking for Senior Design Verification Engineer for our client in Ottawa ... , ON Job Title: Senior Design Verification Engineer Job Location: Ottawa, ON Job ... /Maintain tests for functional verification with UVM verification at the subsystem level ...
15 days ago
... : Job Title: System IP Design Verification Engineer Duration: 6 Months Location: Austin, TX ... a Senior Staff System IP Design Verification Contractor you will contribute to ... the functional verification of System IP including coherent ...
20 days ago
$50
$65
an hour
Description: Title: Mixed-Signal Design Verification Engineer Location: San Jose, CA Key ... , Python, Synopsys/Cadence EDA Verifications Tools, AMS Verification Required Experience/Skills: Good ...
14 days ago
Description: Systems Hardware Architect / Design Verification Engineer Mountain View, CA NO 14+ ... requirementsBuild UVM/System Verilog-based verification environments for IP/subsystem/SoC ...
14 hours ago
... an immediate requirement for a Design Verification Engineer with a client in Mountainview, CA ... me at . Job Title: Design Verification Engineer Location: Mountain View, CA (Working ...
4 days ago
Description: Title: Pre-Silicon Verification Engineer Contract Length: Initial 6-month contract ( ...
7 days ago
Description: Role: Mixed-Signal Verification Engineer Location: San Jose, CA 100% ...
13 days ago
... and implement IP/SoC verification plans, build verification test benches to enable ... IP/sub-system/SoC level verification. Develop functional tests based on ... verification test plan. Drive Design Verification to closure based ...
14 days ago
Description: Job Title: Design Verification (DV) EngineerLocation: Bay Area, CAJob ... seeking a highly skilled Design Verification (DV) Engineer to join our team in ... background in Networking and SERDES verification. This role requires expertise in ...
13 days ago
Description: Contract Length: Initial 6-month contract (potential to go 18-months) Location:100% onsite in either Sunnyvale, CA, San Francisco, CA or Austin TX Industry: Social Media Work Authorization: Prefers G.C or U.S Citizen. Minimum Requirements ...
7 days ago
Description: Should be good in hands-on using SV/UVM. AMBA (especially AXI is a must) Experience in updating sequence, test, running and debugging Experience in PCIE or C based is a plus
7 days ago
Description: Vendor referrals and C2C will not be considered. Project, main deliverables: Support FPGA debug, simulation and test activities for existing platforms for defined features/escalations Create updated RTL design for identified issues and block ...
18 days ago
... simulation and/or formal-based verification environments at IP and SoC ... -level. Lead and manage verification teams, including planning, execution, tracking ... programs. Develop and execute comprehensive verification plans, including testbenches and test ...
12 days ago
Description: Job Title: PCIe Engineer (Peripheral Component Interconnect Express) ... Engineering Required Skills: Pre-silicon verification / UVM methodology Key Responsibilities: ... SoC-level. Lead and manage verification teams, including planning, execution, ...
7 days ago