Description: FPGA Design Verification Engineer (OVM - UVM design verification ... POSITION: FPGA Design Verification Engineer (OVM - UVM design ... Questa) in Dedham, MA SECURITY CLEARANCE: Must be able ... to obtain Secret Security Clearance (ship is Required ...
a day ago
... REQUIREMENTS: Department of Defense Secret security clearance is required at time ... will be subject to a U.S. Government security investigation and must meet eligibility ...
6 hours ago
... company * Senior FPGA Design Verification Engineer - Secret Clearance * Please apply ONLY ... . We can ONLY consider your application if you have: 1: Active DOD ...
6 days ago
$101,459
a year
... Current registration as an Engineer Intern (EI), Engineer in Training (EIT), ... eminence provision as a manufacturing engineer typically would be rated eligible ... Providing technical advice on contract application/development changes. Leadership experience ...
7 days ago