Description: FPGA Design Verification Engineer (OVM - UVM design verification, FPGA - ASIC design, bash, csh, Perl ... POSITION: FPGA Design Verification Engineer (OVM - UVM design verification, FPGA - ASIC design, bash, csh ...
6 hours ago
... technology solutions company * Senior FPGA Design Verification Engineer - Secret Clearance * Please apply ...
5 days ago
$101,459
a year
... Current registration as an Engineer Intern (EI), Engineer in Training (EIT), ... Creditable specialized experience includes: Applying software engineering/analysis principles, concepts, ... technical support for embedded software, missile systems, and sensor ...
6 days ago