Description: Role Title: Memory PHY RTL Design Engineer Location: Boxborough, MA (Hybrid - 3 days ... Memory PHY team is looking for a passionate and experienced Design Engineer for RTL ... definition, design and development phase of industry-leading Memory PHYs ...
a day ago
... Range: $55hr - $70hr Responsibilities: RTL design for memory I/O. PHY Digital Architecture development from pathfinding ... . CollaboXX with architects, hardware engineers, and firmware engineers to understand the new ...
a day ago