Description: Embedded SW Validation Engineer _ 4+ yrs exp - Onsite @ Palo Alto, ... risks at component and module level. You will be collaborating with ...
5 days ago
... CA As a Sr. physical design engineer, you will contribute to all ... both the block and subchip levels, as well as the ... full-chip level from RTL to GDSII. ... collaborate with the Foundry Process Engineer, SoC Architect, Microarchitecture, Packaging, ...
26 days ago