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Senior director for rtl design jobs in San Jose (8 jobs)

Fpga verification engineer
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FPGA Verification Engineer

  • Zachary Piper Solutions, LLC
  • San Jose
... functionality of a digital design environment for FPGA design using Verilog and UVM ... . Collaborate closely with RTL designers to debug and resolve design issues. Ind
4 days ago

FPGA Verification Engineer

  • Zachary Piper Solutions, LLC
  • San Jose
... functionality of a digital design environment for FPGA design using Verilog and UVM ... . Collaborate closely with RTL designers to debug and resolve design issues. Ind
5 days ago

FPGA Verification Engineer

  • Zachary Piper Solutions, LLC
  • San Jose
... functionality of a digital design environment for FPGA design using Verilog and UVM ... . Collaborate closely with RTL designers to debug and resolve design issues. In
8 days ago

FPGA Verification Engineer

  • Zachary Piper Solutions, LLC
  • San Jose
... functionality of a digital design environment for FPGA design using Verilog and UVM ... . Collaborate closely with RTL designers to debug and resolve design issues. In
11 days ago

FPGA Verification Engineer

  • Zachary Piper Solutions, LLC
  • San Jose
... functionality of a digital design environment for FPGA design using Verilog and UVM ... . Collaborate closely with RTL designers to debug and resolve design issues. In
16 days ago

FPGA Verification Engineer

  • Zachary Piper Solutions, LLC
  • San Jose
... will focus on verifying FPGA designs in routers, ensuring all functionalities ... verification, and collaborating closely with RTL designers to debug failures. The ...
2 days ago

FPGA Verification Engineer

  • Zachary Piper Solutions, LLC
  • San Jose
... will focus on verifying FPGA designs in routers, ensuring all functionalities ... verification, and collaborating closely with RTL designers to debug failures. The ...
9 days ago

FPGA Verification Engineer

  • Zachary Piper Solutions, LLC
  • San Jose
... will focus on verifying FPGA designs in routers, ensuring all functionalities ... verification, and collaborating closely with RTL designers to debug failures. The ...
13 days ago

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