Description: Role: Design Verification Engineer Work Location: San Francisco, CA - ...
22 days ago
Description: Looking for Lead layout design for high-performance analog cores (ADCs, DACs, PLLs, transceivers) in CMOS process nodes (5nm to 65nm). Set up LVS, DRC, and ERC environments, debug using Cadence and Mentor tools. Perform floor planning, ...
15 hours ago