Description: Role: Design Verification Engineer Work Location: San Francisco, CA - ...
27 days ago
Description: Required: Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog Experience in developing micro architectural document from requirements specifications Experience developing designs from scratch ...
2 days ago
Description: Looking for Lead layout design for high-performance analog cores (ADCs, DACs, PLLs, transceivers) in CMOS process nodes (5nm to 65nm). Set up LVS, DRC, and ERC environments, debug using Cadence and Mentor tools. Perform floor planning, ...
5 days ago