Description: RTL ASIC Design Design/ Architecture design (ONSITE,CA) Location: Sunnyvale Fulltime ... components Digital design, using System Verilog and/or Verilog RTL, RTL generators (in ... or high-level synthesis ("HLS"). RTL integration of SoC subsystems, IPs ...
29 days ago
... library componentsDigital design, using System Verilog and/or Verilog RTL, RTL generators (in ... /or high-level synthesis ( HLS ). RTL integration of SoC subsystems, IPs ... componentsSoC-level integrationSupport mapping of RTL on Zebu and HAPS for ...
29 days ago
Description: Role: Design verification EngineerLocation: Sunnyvale or Austin, ... , error, and connectivity, both for RTL and Gate Level Netlist Design Unde
5 days ago
... Description: Position: UX Designer/Art Director Location: Sunnyvale, CA Duration: ... usability testing, and data-driven design decisions. Develop wireframes, prototypes, ... Optimize information architecture and interaction design for seamless digital experiences. ...
25 days ago
Description: Senior Electrical Engineer - Advanced ... are seeking a highly experienced Senior Product Lead with a robust ... Semiconductor Electronics and ASIC Design. The ideal candidate ... knowledge in mixed-signal design, chiplet design, and advanced packaging. ...
3 days ago
... : Job Summary: We are seeking a Senior Java Spark Developer with expertise ... the Cloudera Hadoop Ecosystem to design and develop large-scale data ...
a day ago
... : Job Summary: We are seeking a Senior Java Spark Developer with expertise ... the Cloudera Hadoop Ecosystem to design and develop large-scale data ...
3 days ago
... Job Responsibilities: As a Senior Data Engineer, you will Design and develop big ...
a day ago