Description:
Design Verification Engineer - CPU Subsystem Looking for a Design Verification Engineer to play a key role in ensuring the quality & reliability of the companies IP solutions. Requires strong expertise in System Verilog (SV) & UVM, with a focus on developing verification environments, executing test plans, & driving functional verification at the RTL level. The ideal person would have experience with coverage analysis, UVC development, & verification of complex protocols like AXI & CHI, with ad
Feb 18, 2025;
from:
dice.com