Description:
Position Title: Design Verification Engineer Location: Mountain View, CA - Onsite Role Duration: 12+ months contact Below 14+ yrs profiles only Key Responsibilities: Strong understanding of SV and UVM and good debugging skills. Understanding of AMBA protocols. Understand design specs and develop test plans based on functional and architectural requirements Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing Develop directed and random testcases, perform
Apr 3, 2025;
from:
dice.com