Description:
What we are looking for: Bachelor s degree in electronic engineering, or the equivalent qualification in training and experience. 8+ yrs of professional engineering experience, including experience in advanced technology nodes: 28nm, 16nm and below. Familiar with industry standard CAD methodologies from Cadence, Synopsys, and/or Mentor. Successful execution of timing constraint development in previous projects. Solid analytical, communication and presentation skills. Timing Constraint, RTL Codin
Apr 7, 2025;
from:
dice.com