Description:
Job Title: Chip-Level Timing Constraint Development EngineerLocation: San Jose, CA - You must be already located in the San Jose area. Duration: 12+ MonthsVisa: Open (No restrictions) Responsibilities: 5 years of experience Define, develop, and validate timing constraints (SDC) for complex chip-level ASIC designs Perform static timing analysis (STA) to ensure full timing coverage and closure Collaborate with RTL, architecture, and physical design teams on clock structures and design intent Opti
Apr 24, 2025;
from:
dice.com