Where

ASIC/RTL Design Engineer - Senior at San Jose, CA

Infobahn Softworld Inc.
Santa Clara Full-day Temporary

Description:

TOP 3 SKILLS: Good understanding of SystemVerilog, analyzing existing designs and making modifications, able to understand tools used by ASIC engineers like Lint, CDC, STA, etc. - scripting is nice to have KEY RESPONSIBILITIES: Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements. Collaborate with architecture and hardware teams to understand the requirements. Work with verification and p
May 30, 2025;   from: dice.com

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