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Design verification pcie jobs in San Francisco (4 jobs)

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CAD/EDA Engineer Silicon Design/Verification Infrastructure

  • PDDN Inc
  • San Francisco
... : Role: CAD/EDA Engineer Silicon Design/Verification Infrastructure Location: San Francisco, CA ... EDA/CAD SoC/IP design and/or verification infrastructure development. Proficiency in ... experience. Knowledge of ASIC/SoC design flows, SystemVerilog, and UVM. ...
30 days ago

Senior Design Verification Engineer SV/UVM

  • Advantra Consulting Group
  • San Francisco
Description: Senior Design Verification Engineer SV/UVM Contract Long ... francisco BayArea Key ResponsibilitiesOwn the verification of complex IP/subsystems using ...
15 days ago

Verification Engineer role in Bay Area, CA/Austin, TX (Onsite)

  • Yochana IT Solutions
  • San Francisco
Description: Should be good in hands-on using SV/UVM. AMBA (especially AXI is a must) Experience in updating sequence, test, running and debugging Experience in PCIE or C based is a plus
24 days ago

Static Timing Analysis (STA) Engineer

  • IT Trailblazers, LLC
  • San Francisco
... verification and closure of high-performance ASICs, SoCs, and custom semiconductor designs ... timing analysis, debugging violations, optimizing designs for performance, and working closely ... with physical design and RTL teams to achieve ...
10 days ago

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