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Failure analysis engineer jobs in Santa Clara (2 jobs)

Design verification engineer - cpu subsystem
dice.com
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Design Verification Engineer - CPU Subsystem

  • Yoh - A Day & Zimmerman Company
  • Santa Clara
... Subsystem Looking for a Design Verification Engineer to play a key role in ... would have experience with coverage analysis, UVC development, & verification of complex ...
a day ago

Design Verification Engineer - CPU Subsystem

  • Yoh - A Day & Zimmerman Company
  • Santa Clara
... Subsystem Looking for a Design Verification Engineer to play a key role in ... would have experience with coverage analysis, UVC development, & verification of complex ...
22 days ago

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